advance product brief march 1997 LUC4AS01 atm switch element (asx) section 5.4 lucent technologies?roprietary use pursuant to company instructions introduction the asx ic is part of the atlanta chip set consist- ing of four devices that provide a highly integrated, innovative, and complete vlsi solution for imple- menting the atm layer core of an atm switch system. the chip set enables construction of high-perfor- mance, feature-rich, and cost-effective atm switches, scalable over a wide range of switching capacities. this document discusses the asx device. features n functions as a highly ef?ient, 5 gbits/s, shared memory, atm switching element for scalable switch fabrics up to 25 gbits/s. ?in stand-alone mode, used as an 8 x 8 switch fabric with 622 mbits/s i/o rates. ?can be used as a building block for larger n x n fabrics of up to 40 x 40 ports with 622 mbits/s i/o rate (25 gbits/s total atm throughput). ?in three-stage mode, supports variable expan- sion factors (4:8, 5:8, and 6:8) for more compact fabric design with higher port density. n works with other atlanta devices to provide total system solutions for atm switching. ?directly interfaces with the luc4ab01 atm buffer manager (abm) chip to support port card buffering. ?directly interfaces with the luc4ac01 atm crossbar element (ace) chip for constructing larger nonblocking, lossless, and self-routing switch fabrics, organized into a three-stage topology. n incorporates a novel internal backpressure algo- rithm based on separate on-chip queues for all fab- ric ports to enable large scale cell buffers on the port cards (up to 32k cells per port) using cost- effective commonly available srams. n has an internal 512 cell memory, fully shared across all queues, supplemented by the port card buffers. n supports four delay priorities per queue and uses a programmable, weighted, round-robin scheduler for servicing delay priorities. n provides ef?ient unrestricted multicasting with single copy storage. n incorporates independent clocking of input ports to facilitate robust distributed systems designs by allowing for independent port card clocks or arbi- trary clock skew introduced across backplanes from separate port cards. n uses differential clocking to provide noise immu- nity. parity and cell insertion/extraction aid in detecting and tracking system errors. n provides system diagnostic features, including detection and reporting of the following error condi- tions: ?input port parity error. ?input port overrun error. ?loss of input port clock. ?crc error on outgoing cell. ?linked list fault indication. ?test cell extraction. n provides several performance/traf? indicators. n supports a generic intel * or motorola ? compatible 16-bit microprocessor interface with interrupt. n facilitates circuit board testing with on-chip ieee standard boundary-scan. n fabricated as a low-power monolithic ic in 0.5 m m, 3.3 v cmos technology, with 5 v tolerant and ttl- level compatible i/o. n available in a 388-pin pbga package. * intel is a registered trademark of intel corporation. ? motorola is a registered trademark of motorola, inc. ? ieee is a registered trademark of the institute of electrical and electronics engineers, inc.
2 2 lucent technologies inc. advance product brief march 1997 atm switch element (asx) LUC4AS01 section 5.4 lucent technologies?roprietary use pursuant to company instructions description figure 1 shows the architecture of an atm switch designed with the atlanta chip set. this document summarizes atlanta switch fabrics and the LUC4AS01 atm switch element (asx). the atlanta asx device provides the switching function for an atm switch fabric. this 8 x 8 switch element functions as a complete 5 gbits/s switch fabric with oc-12 equivalent port rates, or as a building block for larger three stage switch fabrics (up to 40 x 40 oc-12 equivalent ports, 25 gbits/s systems). the asx interfaces directly to both the atlanta luc4ac01 atm crossbar element (ace) device (for linking switch elements) and the luc4ab01 atm buffer manager (abm) device (for buffer management). high-performance, nonblocking, lossless, and self-routing switch fabrics can be con- structed using the atlanta chip set. 5-4554r9 figure 1. architecture of an atm switch using the atlanta chip set alm luc4au01 microprocessor interface sram line card #1 #1 #1 line card #n n x n switch fabric #n backplane redundant backplane abm luc4ab01 sram physical layer interface (mphy) alm luc4au01 sram abm luc4b01 sram asx LUC4AS01 ace luc4ac01 asx LUC4AS01 asx LUC4AS01 ace luc4ac01 asx LUC4AS01 #1 #1 #n n x n redundant switch fabric #n asx LUC4AS01 ace luc4ac01 asx LUC4AS01 asx LUC4AS01 ace luc4ac01 asx LUC4AS01 #1 #1 #n ingress direction egress direction #1 #1 #n #n #n #n 1 m phy ports 1 m phy ports microprocessor interface microprocessor interface microprocessor interface
lucent technologies inc. 3 advance product brief march 1997 atm switch element (asx) LUC4AS01 section 5.4 lucent technologies?roprietary use pursuant to company instructions description (continued) the asx has an internal 512 cell memory, fully shared across all queues; no external sram is required in the fabric. it supports four delay priorities per queue and uses a programmable weighted round-robin algorithm for scheduling delay priority service. novel techniques are incorporated for congestion management. an inno- vative bell labs-developed adaptive dynamic threshold algorithm permits ef?ient buffer sharing while prevent- ing any queue from seizing a disproportionate share of the cell buffer. a novel internal backpressure algorithm is applied to prevent the fabric cell buffer from over?w- ing and increase buffer sharing of large-scale buffers on the port cards using cost-effective, commonly avail- able srams. the asx provides ef?ient unrestricted multicasting with single copy storage. the asx also provides system diagnostic features. diagnostic reports include parity errors on inputs, inter- nal memory overrun errors, and loss of input port clock. in addition, a crc is calculated on data input to the asx, passed through the asx, then calculated after the data is switched to ensure that silicon errors have not been introduced. when a crc error is detected, a parity error is indicated in the data as it is output from the asx. test cell extraction through the microprocessor interface also aids in testability. the asx block diagram and a brief description of the functionality follows. 5-4515ar9 figure 2. asx block diagram input clocking 26 12 12 12 12 12 12 8 (data) 1 (parity) 1 (start of cell) 2 (clock) buffer memory queue test access output 12 12 12 12 12 12 12 12 3 5 8 (data) 1 (parity) 1 (start of cell) 2 (clock) test access port processor input processor input processor input processor input processor input processor input processor input processor 12 12 processor arbiter processor output processor output processor output processor output processor output processor output processor output processor egress ports ingress ports synchronization gtsync system clock microprocessor interface reset (grst) output enable (asxoe) and (bmem) (qp) (arb) configuration and status registers (gclk) first/third stage backpressure (f1t3_1, f1t3_e, f1t3clk) to ace (cb1_m, cb2_n) source 8 feedback generation circuit and cell extraction fifo (mpi) port (jtag)
4 4 lucent technologies inc. advance product brief march 1997 atm switch element (asx) LUC4AS01 section 5.4 lucent technologies?roprietary use pursuant to company instructions description (continued) overview as shown in figure 2, data for each port is clocked into an input processor, passed to internal cell buffers, and then routed to the appropriate output processor. the queue processor, routing and arbitration circuit, and backpressure feedback generation circuit controls the movement of data into and out of the cell buffer mem- ory. control and status is communicated through a 16-bit asynchronous microprocessor interface. figure 3 shows an example 16 x 16 atlanta-based switch fabric. the switch fabric will switch any of the 16 inputs to any of the 16 outputs. this is achieved by staging devices and is referred to as a three-stage switch fabric. the input stage is called the ?st stage (expander), and the output stage is called the third stage (concentrator). the center stage consists of the companion ace device. the ace is functionally similar to the asx, but without the internal cell buffer (a hand- shake protocol between the asx and the ace ensures that the ace need not store data). conceptually, the ?st-stage asx expands the number of paths available for switching the data, while the third stage concen- trates data from the center stage. the asx device sup- ports 4:8, 5:8, and 6:8 expansion modes. the expansion mode is con?urable, depending on cost and performance objectives, as well as the type of traf- ? expected. a three-stage asx/ace based switch fabric can sup- port up to 40 ports with 622 mbits/s i/o rates. a 40-port (25 gbits/s total atm throughput) fabric design would use eight devices per stage in a 5:8 expansion mode. 5-4523r5 figure 3. example 16 x 16 @ 622 mbits/s switch fabric (10 gbits/s throughput) asx module #0 asx module #1 asx module #2 asx module #3 ace module #0 ace module #1 ace module #2 asx module #0 asx module #1 asx module #2 asx module #3 input from port cards output to port cards first-stage expander third-stage concentrator center-stage crossbar ace module #3
lucent technologies inc. 5 advance product brief march 1997 atm switch element (asx) LUC4AS01 section 5.4 lucent technologies?roprietary use pursuant to company instructions description (continued) input processors the input processors are responsible for accepting data onto the device. there are eight input processors, one for each port. any of the inputs can be used regardless of the expansion factor. each input port has eight data bits, one parity bit, one start of cell bit, and a differential clock. the microprocessor must enable the appropriate input ports. the input processor does pre- liminary processing and stores the header, payload, and the internally generated crc-8 of the arriving cell until it can be written to the internal cell buffer. input ports are clocked independently from 10 mhz to 100 mhz. this independent clocking facilitates back- plane based system designs with distributed port cards. the input port interface is designed to minimize the risk of undetected errors. the differential clock provides system noise immunity to prevent errors. in addition, the input processor detects the presence of an input clock and reports when the input clock is lost. the input processor also checks for incoming parity errors. and, an internal crc-8 is generated for each atm cell that is transferred to the internal cell buffer for switching. the crc is then checked before the switched data is transferred off the device. furthermore, the input pro- cessor also detects and reports input port overrun errors. buffer memory the asx contains 512 cells of internal memory. this memory is shared among all active system ports (up to 40). the buffer memory stores the local header, the atm header, and the cell payload until this data can be shifted out to the appropriate output port. output processors the output processors perform many of the same func- tions as the input processor. they handle the postpro- cessing and shifting out of the data. the micro- processor can disable the appropriate output ports. queue processor the queue processor controls the movement of data to/ from the 512 cell buffer memory and maintains buffer memory statistics. there are eight queue controllers within the queue processor. incoming cells are routed to one or more queue controllers. source arbiter the source arbiter (arb) determines which queues will be serviced by the device output ports. the operation of the arbiter depends on whether the device is con?- ured as a stand-alone, ?st stage, or third stage mod- ule. cells may be from different queues or the same queue. up to eight cells can be selected, or one per device output port. the arb also interprets optional egress backpressure information from port cards. microprocessor interface the microprocessor interface (mpi) provides a general 16-bit asynchronous interface to an external processor for accessing the asx con?uration and status regis- ters and internal memory. the mpi also supports per- function, maskable interrupts. the interface operates identically to the interface in the alm, abm, and ace. the mpi is designed to support various 16-bit micro- processors with minimal glue logic, and to directly inter- face to popular intel and motorola microprocessors. test access port the asx incorporates logic to support a standard ?e- pin test access port (tap), compatible with the ieee p1149.1 standard (jtag), used for boundary scan. tap contains instruction registers, data registers, and control logic, and has its own set of instructions. it is controlled externally by a jtag bus master. the tap gives the asx board-level test capability.
advance product brief march 1997 atm switch element (asx) LUC4AS01 for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro u.s.a.: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106), e-mail docmaster@micro.lucent.com asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singapore 118256 tel. (65) 778 8833 , fax (65) 777 7495 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 for data requests in europe: microelectronics group dataline: tel. (44) 1734 324 299 , fax (44) 1734 328 148 for technical inquiries in europe: central europe: (49) 89 95086 0 (munich), northern europe: (44) 1344 865 900 (bracknell uk), france: (33) 1 41 45 77 00 (paris), southern europe: (39) 2 6601 1800 (milan) or (34) 1 807 1700 (madrid) lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. copyright ?1997 lucent technologies inc. all rights reserved printed in u.s.a. march 1997 pn96-065atm printed on recycled paper
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